? semiconductor components industries, llc, 2009 february, 2009 ? rev. 2 1 publication order number: nb7l14md nb7l14 2.5v / 3.3v 7ghz/10gbps differential 1:4 lvpecl fanout buffer multi ? level inputs w/ internal termination description the nb7l14 is a differential 1:4 lvpecl fanout buffer. the nb7l14 produces four identical lvpecl output copies of clock or data operating up to 7 ghz or 10.7 gb/s, respectively. as such, the nb7l14 is ideal for sonet, gige, fiber channel, backplane and other clock or data distribution applications. the differential inputs incorporate internal 50 termination resistors that are accessed through the vt pin. this feature allows the nb7l14 to accept various logic standards, such as lvpecl, cml, lvds, lvcmos or lvttl logic levels. the v refac reference output can be used to rebias capacitor ? coupled differential or single ? ended input signals. the 1:4 fanout design was optimized for low output skew applications. the nb7l14 is a member of the gigacomm ? family of high performance clock products. features ? input data rate > 10.7 gb/s ? input clock frequency > 7 ghz ? 165 ps typical propagation delay ? 45 ps typical rise and fall times ? <15 ps max output skew ? <0.8 ps maximum rms clock jitter ? <15 ps pp of data dependent jitter ? differential lvpecl outputs, 720 mv peak ? to ? peak, typical ? lvpecl operating range: v cc = 2.375 v to 3.6 v with gnd = 0 v ? necl operating range: v cc = 0 v with gnd = ? 2.375 v to ? 3.6 v ? internal input termination resistors, 50 ? v refac reference output ? functionally compatible with existing 2.5 v / 3.3 v lvel, lvep, ep, and sg devices ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices http://onsemi.com *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g see detailed ordering and shipping information in the package dimensions section on p age 8 of this data sheet. ordering information (note: microdot may be in either location) 16 nb7l 14 alyw 1 xxxx = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package ?? ?? figure 1. logic diagram 50 50 in vt in q3 q3 q2 q2 q1 q1 q0 q0 v refac
nb7l14 http://onsemi.com 2 gnd q3 q3 v cc gnd q0 q0 v cc q1 q1 q2 q2 in vt v refac in 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb7l14 exposed pad (ep) figure 2. qfn ? 16 pinout (top view) table 1. pin description pin name i/o description 1 in ecl, cml, lvcmos, lvds, lvttl input non ? inverted differential input. note 1. internal 50 resistor to termination pin, vt 2 vt ? internal 50 ? termination pin for in/in inputs. 3 vrefac output reference voltage for capacitor ? coupled inputs 4 in ecl, cml, lvcmos, lvds, lvttl input inverted differential input. note 1. internal 50 resistor to termination pin, vt. 5 gnd ? negative supply voltage 6 q3 lvpecl output inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 7 q3 lvpecl output non ? inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 8 vcc ? positive supply voltage 9 q2 lvpecl output inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 10 q2 lvpecl output non ? inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 11 q1 lvpecl output inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 12 q1 lvpecl output non ? inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 13 vcc ? positive supply voltage 14 q0 lvpecl output inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 15 q0 lvpecl output non ? inverted differential output. typically terminated with 50 resistor to v cc ? 2.0 v. 16 gnd ? negative supply voltage ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for im- proved heat transfer out of package. the exposed pad must be attached to a heat ? sinking con- duit. the pad is electrically connected to the die, and must be electrically connected to device gnd. 1. in the dif ferential configuration when the input termination pin (vt) is connected to a common termination voltage or left op en, and if no signal is applied on in/in input, then, the device will be susceptible to self ? oscillation. 2. all vcc and gnd pins must be externally connected to a power supply for proper operation.
nb7l14 http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model > 2.0 v > 150 v moisture sensitivity (note 3) qfn ? 16 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 173 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v ? 0.5 v to +4.0 v v io positive input/output voltage gnd = 0 v ? 0.5 v io v cc + 0.5 4.0 v v inpp differential input voltage |d ? d | 2.8 v i in input current through r t (50 resistor) 40 ma i out output current (lvpecl output) continuous surge 50 100 ma i vfrefac v refac sink/source current 1.5 ma t a operating temperature range qfn ? 16 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w jc thermal resistance (junction ? to ? case) (note 4) qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb7l14 http://onsemi.com 4 table 4. dc characteristics, multi ? level inputs v cc = 2.375 v to 3.6v, gnd = 0 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit power supply current v cc power supply voltage v cc = 2.5 v v cc = 3.3 v 2.375 3.0 2.5 3.3 2.625 3.6 v i cc power supply current (inputs and outputs open) 85 105 ma lvpecl outputs (notes 5 & 6) v oh output high voltage v cc = 2.5v v cc = 3.3v v cc ? 1145 1355 2155 v cc ? 900 1600 2400 v cc ? 825 1675 2475 mv v ol output low voltage v cc = 2.5 v v cc = 3.3 v v cc ? 2000 500 1300 v cc ? 1700 800 1600 v cc ? 1500 1000 1800 mv differential input driven single ? ended (see figure 5 & 7) (note 7) v ih single ? ended input high voltage v th + 75 v cc mv v il single ? ended input low voltage gnd v th ? 75 mv v th input threshold reference voltage range (note 8) 1125 v cc ? 75 mv v ise single ? ended input voltage amplitude (v ih ? v il ) 150 2800 mv vrefac v refac output reference voltage (100 a load) v cc ? 1400 v cc ? 1300 v cc ? 1000 mv differential inputs driven differentially (see figure 6 & 8) (note 9) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage 0 v ihd ? 50 mv v id differential input voltage (v ihd ? v ild ) 100 2800 mv v cmr input common mode range (differential configuration) (note 10) (figure 9) 950 v cc ? 50 mv i ih input high current in / in , (vt open) ? 150 150 a i il input low current in / in , (vt open) ? 150 150 a termination resistors r tin internal input termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. lvpecl outputs loaded with 50 to v cc ? 2.0 v for proper operation. 6. input and output parameters vary 1:1 with v cc . 7. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 8. v th is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 10. v mr min varies 1:1 with v ee , v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb7l14 http://onsemi.com 5 table 5. ac characteristics v cc = 2.375 v to 3.6 v, gnd = 0 v, ta = ? 40 c to +85 c ; (note 11) symbol characteristic min typ max unit f max maximum input clock frequency; v out 400 mv 7 8 ghz f datamax maximum operating data rate; nrz, (prbs23) 10 11 gbps v outpp output voltage amplitude (note 15) f in 5 ghz (see figure 9) f in 7 ghz 500 400 720 450 mv t plh , t phl propagation delay in to q 125 165 200 ps t skew duty cycle skew (note 12) output ? output within device skew device to device skew 3 15 15 50 ps t dc output clock duty cycle f in 7 ghz (reference duty cycle = 50%) 45 50 55 % t jitter rms random clock jitter (note 13) f in 7 ghz peak ? to ? peak data dependent jitter (note 14) f in 10.7 gb/s 0.5 5 0.8 15 ps rms ps pk ? pk v inpp input voltage swing/sensitivity (differential configuration) (note 15) 100 1200 mv t r t f output rise/fall times @ 1.0 ghz qx, qx (20% ? 80%) 30 45 60 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured by forcing v inpp (min) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 12. skew is measured between outputs under identical transitions and conditions @ 0.5 ghz. duty cycle skew is measured between dif ferential outputs using the deviations of the sum of t pw ? and t pw + @ 0.5 ghz. 13. additive rms jitter with 50% duty cycle clock signal. 14. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23. 15. input and output voltage swing is a single ? ended measurement operating in differential mode. figure 3. clock output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typ) f in , clock input frequency (ghz) output voltage amplitude (mv) 800 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 q amp (mv) figure 4. input structure 50 50 v t v cc in in 700 600 500 400 300
nb7l14 http://onsemi.com 6 in v th in v th figure 5. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th in in v ildmax v ihdmax v ihdtyp v ildtyp v ihdmin v ildmin v cmr gnd v id = v ihd ? v ild v cc in in q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (in) ? v il (in) v ihd v ild v id = |v ihd(in) ? v ild(in)| in in figure 6. differential inputs driven differentially figure 7. v th diagram figure 8. differential inputs driven differentially figure 9. v cmr diagram figure 10. ac reference measurement in in v cmmax v cmmin
nb7l14 http://onsemi.com 7 lvpecl driver v cc gnd z o = 50 v t = v cc ? 2 v z o = 50 nb7l14 in 50 50 in gnd figure 11. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 nb7l14 in 50 50 in gnd figure 12. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 nb7l14 in 50 50 in gnd v cc figure 13. standard 50 load cml interface differential driver v cc gnd z o = 50 v t = v refac * z o = 50 nb7l14 in 50 50 in gnd v cc figure 14. capacitor ? coupled differential interface (vt connected to external v refac ) *v refac bypassed to ground with a 0.01 f capacitor single ? ended driver v cc gnd z o = 50 v t = v refac * nb7l14 in 50 50 in (open) gnd v cc figure 15. capacitor ? coupled differential interface (v t connected to external v refac ) *v refac bypassed to ground with a 0.01 f capacitor
nb7l14 http://onsemi.com 8 figure 16. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? nb7l14mng qfn ? 16 (pb ? free) 123 units / rail NB7L14MNTXG qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7l14 http://onsemi.com 9 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? ?? 0.00 0.15 mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb7l14/d gigacomm is a trademark of semiconductor components industries llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
